GateFlow, Revolutionary FPGA Extendible Product Line, Delivers New FFT with Tenfold Speed Advantage and Eases Custom Algorithm Development

  • FPGA Offloads Computational-Intensive DSP Functions From Processor
  • FFT Core Delivers Spurious Free Dynamic Range Better Than 90 dB
  • FFT Calculation Speed Delivers Real-Time Performance at 100 MHz
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Upper Saddle River, NJ - August 5, 2002 - FPGAs (Field Programmable Gate Arrays) are ideal for implementing the data formatting, timing, and the specialized glue logic needed to connect real-time peripherals like modems, A/D converters digital receivers to programmable processors. However, with their newly-acquired DSP capabilities, FPGAs are now expanding these traditional roles to help offload computationally-intensive digital signal processing functions from the processor.

Today, Pentek, Inc. released GateFlowTM, a family of extendible FPGA products. The GateFlow product line includes GateFlow Installed Cores featuring Pentek's streamlined FFT (Fast Fourier Transform) implemented on the industry's first FPGA-based dual channel wideband receiver, and the GateFlow FPGA Design Kit to facilitate custom algorithm development.

"These latest FPGA devices feature built in hardware multipliers, a large pool of configurable memory, and plenty of system gates and logic blocks. Even after all of the standard data formatting and interfacing functions for the module are incorporated, these FPGAs still offer substantial available resources for signal processing functions," said Rodger Hosking, Vice President of Pentek. "Now engineers can take advantage of this additional FPGA logic in two ways. They can develop their own algorithms using Pentek's GateFlow Design Kit, or have Pentek configure the product with a GateFlow Installed Core FFT. This new high-performance FFT core delivers incredible speed, perfect for applications in radar, wireless and signals intelligence."

Dual Channel Digital Receiver with GateFlow Installed Core FFT

Available as a factory installed option to the Pentek Model 6235 Dual Channel, 12-bit, 100 MHz Wideband Digital Receiver, the GateFlow FPGA FFT engine offers a very powerful front end for many signal processing systems.

The Model 6235 includes two complete acquisition and receiver channels in a VIM-2 (Velocity Interface Mezzanine) module compatible with Pentek's 429x series PowerPC and C6000 VME processor boards. The Model 6235 can be equipped with either the XC2V1000 or XC2V3000 FPGA from the Xilinx Virtex-II family, offering logic densities of 1 or 3 million gates, respectively.

The Model 6235 is the first of many VIM and PMC modules that will offer the highly-optimized GateFlow FFT inside each onboard FPGA. Additional GateFlow Installed Core algorithms are planned for the future.

The Speed of the GateFlow Installed Core FFT

Utilizing a proprietary block memory architecture, the GateFlow FFT executes a pipelined complex 4k-point radix-4 FFT in just 10.24 usec. This is four times faster than the time to collect the 4k input points at a 100 MHz sampling rate. Therefore, with two 100 MHz A/Ds on the Model 6235, the GateFlow FFT can handle both A/Ds with 50% input overlap processing and zero data loss. The execution speed for the 1k-point complex FFT is 2.56 usec, also four times faster than real-time at 100 MHz.

These GateFlow FFT execution speeds are more than ten times faster than an optimized FFT algorithm running on a 400 MHz G4 PowerPC! This delivers a tremendous performance advantage over systems where FFTs are performed on programmable processors.

Noise Reduction and Auxiliary FFT Functions

Several noise reduction techniques were employed to reduce the rounding and truncation errors inherent in FPGA fixed-point arithmetic. The resulting calculation dynamic range of better than 90 dB allows detection of signals that otherwise might be lost. At each of the four complex input streams, an optional Hanning (or alternate) windowing function can be applied. In addition, an optional power calculation is available at the FFT output, which sums the squares of real and imaginary components. Finally, an averager stage adds the two outputs of the 50% input overlap FFTs to further improve signal-to-noise characteristics.

GateFlow FPGA Design Kit

Engineers can now tap into the additional FPGA resources available on Pentek's FPGA-based VIM and PMC narrowband and wideband digital receivers, A/Ds and FPDP I/O modules with Pentek's Model 4953 GateFlow FPGA Design Kit. The Design Kit provides the user with design information, software files and utilities for extending FPGA-functions in these products. Users can implement a variety of custom pre-processing functions such as convolution, framing, pattern, recognition, decompression, delays, beamforming, decoding, time stamping, averaging and summation.

The Design Kit includes the software project used in Xilinx Foundation to create all of the standard factory functions of the product, such as the device and bus interfaces, data formatting, clocking and control. All VHDL source code modules for the standard factory configuration, instructions and utilities for loading a new user-defined configuration to the FPGAs are also included.

Pricing and Availability

For the latest pricing, delivery and available options, please fill out this form and your request will be delivered to the appropriate department. To learn more about our products or to discuss your specific application please email our sales department at, contact your local representative or Pentek directly:

Mario Schiavone
Sales Director
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
Tel: +1 (201) 818-5900
Fax: +1 (201) 818-5904
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