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Model 72751 2-Ch 500 MHz A/D w/ DDC & 2-Ch 800 MHz D/A w/ DUC, Virtex-7 FPGA - 6U cPCI

This product is in the Inactive Life Cycle. Please contact Pentek for additional information.

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  • Complete radar and software radio interface solution
  • Supports Xilinx Virtex-7 VXT FPGAs
  • GateXpress supports dynamic FPGA reconfiguration across PCIe
  • Two or four 500 MHz 12-bit A/Ds
  • Two or four multiband DDCs (digital downconverters)
  • One or two DUCs (digital upconverters)
  • Two or four 800 MHz 16-bit D/As
  • 4 GB of DDR3 SDRAM
  • Sample clock synchronization to an external system reference
  • LVPECL clock/sync bus for multimodule synchronization
  • Optional LVDS connections to the Virtex-7 FPGA for custom I/O
  • Optional 400 MHz 14-bit A/Ds
  • See comparable Jade Xilinx Kintex UltraScale FPGA Module: Model 72851

 

Model 72751

Onyx Xilinx Virtex-7
 

Model 72751 Block Diagram

Please refer to the product datasheet for a larger version of the block diagram


Hardware and Software Manuals - ( top )

Please note that some hardware and software manuals are used for more than one Pentek product. Although the model numbers given in the description of each manual below may vary, these manuals are all used for the product described on this web page.

Part No.
Type
Description
Revision/Date
800.71751 Operating Manual Model 71751 2-Ch A/D w/ 2 DDCs, 2-Ch D/A w/Interp, Onyx Family XMC Module 1.8 (6/28/2016)
801.71750 Programmer's Reference ReadyFlow Board Support Libraries for 71751, 5973/7070-320, 5973/7070-324 3.2 (9/19/2016)
809.7x751 Supplemental Manual Vendor Data Sheets for Model 7x751 Series Operating Manuals 1.1 (5/15/2014)
815.71650 User's Guide Model 4995A Option 165/651/751 Windows ReadyFlow BSP for 7165x, 71751 4.1A (10/10/2017)
816.71650 User's Guide Model 4994A Option 165/651/751 Linux ReadyFlow BSP for 71650, 71651, 71751 4.1 (10/28/2015)



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