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Model 4954-421 GateFlow IP Core Library - Wideband 160 MHz DDC Core

This IP Core is no longer available for individual purchase. It is available installed in Pentek Models 6235, 6236, 7140, 7240, 7340 and 7640.

Block Diagram




Life Cycle Management

Ordering & Warranty


  • IP Core only installed on Pentek FPGA board-level products
  • High-performance wideband digital downconverter (DDC)
  • Supports Virtex-II and Virtex-II Pro FPGAs
  • Fits in Virtex-II XC2V1000 or larger
  • Similar to the TI GC1012B with enhanced features
  • Input data 16-bit real or 16-bit complex (I and Q)
  • Maximum input data rate of 160 MHz
  • Maximum input bandwidth of 80 MHz (real input) or 160 MHz (complex input)
  • Fully programmable NCO with 32-bit frequency and phase offset control
  • NCO delivers > 110 dB SFDR
  • Decimation settings of 2, 4, 8, 16, 32, and 64 for complex output
  • Decimation settings of 1, 2, 4, 8, 16, and 32 for real output
  • Decimating FIR filter features up to 1792 taps
  • User-programmable 18-bit FIR filter coefficients
  • Default FIR filter coefficients for 80% and 90% filters
  • Output formatter delivers real, complex, offset, inverted data in 16 or 24 bits


Model 4954-421


Model 4954-421 Block Diagram

Hardware and Software Manuals - ( top )

Please note that some hardware and software manuals are used for more than one Pentek product. Although the model numbers given in the description of each manual below may vary, these manuals are all used for the product described on this web page.

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