Product Focus: Model 71620 Software Radio XMC with Virtex-6 FPGA the First of the Pentek Cobalt® Family
- Supports Xilinx Virtex-6 LXT and SXT FPGAs
- Three 200 MHz, 16-bit A/Ds
- One digital upconverter
- Two 800 MHz, 16-bit D/As
- Up to 1 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM
- Sample clock synchronization to an external system reference
- LVPECL clock/sync bus for multimodule synchronization
- VITA 42.0 XMC compatible with switched fabric interfaces
- LVDS connections to the Virtex-6 FPGA for custom I/O
Model 71620 is the first member of the Cobalt® family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications and radar system. It includes three A/Ds, one upconverter, two D/As, and four banks of memory. The Model 71620 is compatible with the VITA 42.0 XMC format and supports PCI Express Gen. 2 as a native interface.
The front end accepts three full scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/Ds. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.
Digital Upconverter and D/A
A TI DAC5688 DUC (digital upconverter) with two D/As accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors.
If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of x2, x4 and x8.
Xilinx Virtex-6 FPGA
The Model 71620 Cobalt® architecture features a Virtex-6 FPGA. All of the board’s data and control paths are accessible by the FPGA, enabling factory installed functions such as data multiplexing, channel selection, data packing, gating, triggering and memory control. In addition to the built-in functions, users can install their own custom IP for data processing with GateFlow® FPGA Design Resources.
The FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR3 SDRAM or QDRII+ SRAM memory, PCIe interface, programmable LVDS I/O, and clock, gate and synchronization circuits.
The FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-6 LX130T, LX240T, or SX315T.
Clocking and Synchronization
Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.
Each timing bus includes a clock, sync, and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by the clock synthesizer circuit to provide different A/D and D/A clocks.
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