Product Focus: Model 7153 4-Channel Beamformer w/four 200 MHz 16-bit A/Ds Ideal for Radar and Software Radio
- Built-in Beamformer supports multiboard systems
- Programmable Power Meter and Threshold Detect per channel
- Four 200 MHz, 16-bit A/Ds
- 2 or 4 Channels of DDC
- Independent DDC tuning and decimation factors for each channel
- DDC decimation range from 2 to 256 or from 2 to 65536
- Default filters offer 0.2 dB ripple and 100 dB rejection
- LVPECL clock/sync bus for multimodule synchronization
Model 7153 is a 4-channel, high-speed
software radio module designed for processing
baseband RF or IF signals. It features
four 200 MHz 16-bit A/Ds supported by a
high-performance 4-channel DDC (digital
downconverter) and a complete set of beamforming
functions. With built-in multiboard
synchronization, it is ideally matched to the
requirements of real-time software radio
and radar systems.
The front end accepts four full-scale
analog RF or IF inputs on front panel SMC
connectors at +8 dBm into 50 ohms with
transformer coupling to four Texas Instruments
ADS5485 200 MHz, 16-bit A/Ds.
The digital outputs are delivered into a
Xilinx Virtex-5 FPGA for routing, formatting
and DDC signal processing operations.
DDC Input Selection and Tuning
The Model 7153 employs an advanced
FPGA-based digital downconverter engine
consisting of two or four DDC channels.
Four independently controllable input multiplexers
select one of the four A/Ds as the
input source for each DDC channel. In this
way, many different configurations can be
achieved including one A/D driving all four
DDC channels and each of the four A/Ds
driving its own DDC bank.
Decimation and Filtering
Each of the four DDC channels can
have its own unique decimation setting,
supporting as many as four different output
bandwidths for the board. The DDC core
can be configured in four-channel mode with
each channel offering decimations between
2 and 256, or in two-channel mode with each
channel having a decimation range of 2 to
65536, for applications that require a wider
range of decimations.
The decimating filter for each DDC
channel accepts a unique set of user-supplied
18-bit coefficients. The 80% default filters
deliver an output bandwidth of 0.8*ƒs/N,
where N is the decimation setting. The
rejection of adjacent-band components within the 80% output bandwidth is better
than 100 dB.
In addition to the DDCs, the 7153 features
a complete beamforming subsystem.
Each channel contains programmable I & Q
phase and gain adjustments followed by a
power meter that continuously measures the
individual average power output. The time
constant of the averaging interval for each
meter is programmable up to 8 ksamples.
The power meters present average power
measurements for each channel in easy-toread
In addition, each channel includes a
threshold detector to automatically send
an interrupt to the processor if the average
power level of any DDC falls below or
exceeds a programmable threshold.
A programmable summation block provides
summing of any of the four output
channels. An additional programmable gain
stage compensates for summation change
bit growth. A power meter and threshold
detect block is provided for the summed
output. The output is then directed to the
Channel 1 FIFO for reading over PCI-X. For
larger systems, multiple 7153's can be
chained together via a built-in Xilinx Aurora
interface through the P15 XMC connector.
For more information and price quotation on the Model 7153, click here.