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Home > Pipeline Vol. 17 No. 3 > Product Focus: Model 7152 Printer Friendly Version

Fall 2008 Vol. 17, No. 3

Model 7153 2- or 4-Channel Digital Downconverter with four 200 MHz, 16-bit A/Ds - PMC/XMC


  • 2 or 4 DDC channels
  • Four 200 MHz, 16-bit A/Ds
  • Independent 32-bit DDC tuning for all channels
  • DDC decimation range from 2 to 256 or from 2 to 65536
  • Independent decimation factors for each channel
  • User-programmable 18-bit FIR filter coefficients
  • Default filters with 0.2 dB ripple and 100 dB rejection
  • Clock/sync bus for multimodule synchronization

General Information

Model 7153 is a 4-channel high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel installed DDC (digital downconverter) IP core and interfaces ideally matched to the requirements of real-time software radio and radar systems.

The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling to four TI ADS5485 200 MHz, 16-bit A/Ds converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

DDC Input Selection and Tuning

The Model 7153 employs an advanced FPGA-based digital downconverter engine consisting of two or four DDC channels. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC channel. Many different configurations can be achieved including one A/D driving all four DDC channels and each of the four A/Ds driving its own DDC bank.

Decimation and Filtering

Each of the four DDC channels can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. The DDC core can be configured in four-channel mode with each channel offering decimations between 2 and 256; or in two-channel mode with each channel having a decimation range of 2 to 65536, for applications that require a wider range of decimation.

The decimating filter for each DDC channel accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒs/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of ƒs/N.

Power Meters, Summation Block

Each channel contains a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 128K samples. The power meters present average power measurements for each channel in easy-to-read registers.

In addition, each channel includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.

A programmable summation block provides summing of any of the four output channels. The summed output is directed to the Channel 1 FIFO for reading over the PCI-X Bus. For larger systems, multiple 7153s can be chained together via a builtin Xilinx Aurora interface through the P15 XMC connector. This allows summation across channels on multiple boards, ideal for beamforming applications.

For more information and price quotation on the Model 7153, click here.


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