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Model 7751D Octal 200 MHz, 16-bit A/D, 512-Channel DDC - PCIe

Block Diagram Datasheet Manuals Development Systems Literature Life Cycle Management Ordering & Warranty Catalogs

512 DDC channels Eight 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each 64-channel DDC bank Each DDC bank independently selects one of eight A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization

Hardware and Software Manuals - ( top )

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