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ATLANTA, GA, Embedded Tech Trends - January 27, 2020 - Pentek, Inc., today introduced the Quartz Model 5550, an eight-channel A/D and D/A converter, 3U OpenVPX board based on the Xilinx Zynq UltraScale+ RFSoC and aligned to the SOSA Technical Standard. The Model 5550 is ideal for many communications, electro-optical, electronic warfare, radar and signals intelligence applications.
"The Model 5550 is leading the industry in the rollout of products developed in alignment with the Technical Standard for the SOSA Reference Architecture," said Bob Sgandurra, director of Product Management of Pentek. "Pentek continues to be very active in the development of the SOSA technical standard and we are now demonstrating our commitment with supporting products and demonstrations."
A key development breakthrough was the decision to implement connector technology that enables one of the major goals of SOSA reference architecture--backplane only I/O. The Model 5550 incorporates the ANSI/VITA 67.3D VPX Backplane Interconnect standard for both coaxial RF and optical I/O. In addition, the Model 5550 includes a 40GigE interface and a shelf-management sub-system that are also required in the SOSA reference architecture.
Pentek's modular approach to hardware and software enables quick adaptation to new and changing customer requirements. The Model 5550 uses the Model 6001 QuartzXM eXpress module containing the RFSoC FPGA and all needed support circuitry implemented on a carrier module designed specifically to align with the technical standard for the SOSA reference architecture. This allows easy upgrades to third generation RFSoC modules when available.
The Model 5550 is pre-loaded with a suite of Pentek IP modules to provide data capture and processing solutions for many common applications. Modules include DMA engines, DDR4 memory controller, test signal and metadata generators, data packing and flow control. The board comes pre-installed with IP for triggered waveform and radar chirp generation, triggered radar range gate selection, wideband real-time transient capture, flexible multi-mode data acquisition and extended decimation. For many applications, the Model 5550 can be used out-of-the-box with these built-in functions, requiring no FPGA development.
The front end accepts analog IF or RF inputs on eight coax connectors located within a VITA 67.3D backplane connector. After balun coupling to the RFSoC, the analog signals are routed to eight 4 GSPS, 12-bit A/D converters. Each converter has built-in digital downconverters with programmable 1x, 2x, 4x and 8x decimation and independent tuning. The A/D digital outputs are delivered into the RFSoC programmable logic and processor system for signal processing, data capture or for routing to other resources. A stage of IP based decimation provides another 16x stage of data reduction, ideal for applications that need to stream data from all eight A/D's.
Eight 4 GSPS, 14-bit D/A converters deliver balun-coupled analog outputs to a second VITA 67.3D coaxial backplane connector. Four additional 67.3D coaxial backplane connections are provided for clocks and timing signals.
The Model 5550 also uses the VITA-67.3D backplane connector for eight 28 Gb/sec duplex optical lanes to the backplane. With two built-in 100 GigE UDP interfaces or a user-installed serial protocol in the RFSoC, the VITA-67.3D backplane interface enables gigabit communications independent of the PCIe interface.
The Navigator FDK includes the board's entire FPGA design as a block diagram that can be edited in Xilinx's Vivado tool suite. All source code and complete documentation is included. Developers can integrate their IP along with the factory-installed functions or use the Navigator kit to replace the IP with their own. The Navigator FDK Library is AXI-4 compliant, providing a well-defined interface for developing custom IP or integrating IP from other sources.
The Navigator BSP supports Xilinx's PetaLinux on the ARM processors. Users work efficiently using high-level API functions, or gain full access to the underlying libraries including source code. Pentek provides numerous examples to assist in the development of new applications.
The Model 8257 is a low cost 3U VPX chassis ideal for developing applications on Pentek's Model 5550 Quartz RFSoC board. Providing power and cooling to match the Model 5550 in a small desktop footprint, the chassis allows access to all required interfaces and the Model 5901 rear transition module. The Model 8257 can be configured with optional rear-panel dual MPO optical connectors to support the Model 5550's dual 100 GigE interfaces and coaxial RF connectors.
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