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"Recent enhancements to OpenVPX have greatly improved I/O capabilities," said Robert Sgandurra, director of Product Management. "These enhancements play well into Pentek's modular approach to product design by offering optical and RF options for high-performance I/O that perfectly match our product capabilities."
The Model 54851 takes advantage of these VPX I/O options for RF and optical interconnects through the VPX backplane:
Future options for higher density optical and RF connectors are planned as the supporting standards become available. Organizations such as The Open Group Sensor Open Systems Architecture (SOSA") Consortium are specifying additional types and apertures for VITA 67.3.
The Model 54851 can be populated with a range of Kintex UltraScale FPGAs to match specific requirements of the processing task, spanning from the entry-level KU035 (with 1,700 DSP slices) to the high-performance KU115 (with 5,520 DSP slices). The KU115 is ideal for demanding modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, a lower-cost FPGA can be installed.
The Model 54851 also includes a complete multi-board clock and sync engine and a large DDR4 memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 54851 includes optional high-bandwidth connections to the Kintex UltraScale FPGA for custom digital I/O.
With the Xilinx Kintex Ultrascale FPGA, data converters and optical or RF I/O, the Model 54851 becomes an excellent high performance interface to HF or IF ports of a communications or radar system.
The Pentek Jade architecture is based on the Xilinx Kintex UltraScale FPGA, which raises the digital signal processing (DSP) performance by over 50% with equally impressive reductions in cost, power dissipation and weight. Its PCI Gen.3 interface allows access to control and status registers for controlling algorithms, state machines and data flow across the LVDS I/O front panel and carrier board interfaces. A 5 GB bank of DDR4 SDRAM is available for additional functions. The factory-installed DMA controller can sustain 6.4 GB/s data transfers across PCIe.
Pentek's Navigator" Design Suite was designed from the ground up to work with Pentek's Jade architecture and Xilinx's Vivado Design Suite® providing an unparalleled plug-and-play solution to the complex task of IP and control software creation and compatibility. Graphical design entry for Xilinx and Pentek AXI4-compliant IP modules using the Xilinx IP Integrator greatly speeds development tasks. The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs and Navigator BSP (Board Support Package) for creating host applications. Users can work efficiently at the API level for software development and with an intuitive graphical interface for IP design. The Navigator BSP is available for Windows and Linux operating systems.
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