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Upper Saddle River, NJ - December 12, 2011 - Pentek, Inc., today released its highest-performing D/A converter module for RF and IF waveform playback, the Cobalt® Model 71670. The module delivers four independent analog outputs each through its own digital upconverter and 16-bit D/A with sampling rates to 1.25 GHz. An on-board Xilinx Virtex-6 FPGA contains factory-installed IP that provides turnkey waveform playback functionality for output signal bandwidths up to 250 MHz. Users can also customize the module's operation by implementing their own IP in the FPGA.
"With four channels capable of independent translation from baseband to IF frequency," said Rodger Hosking, vice president of Pentek, "the Model 71670 makes a perfect complement to our Cobalt Models 71660 and 71661 four-channel A/D boards. For the first time, this important new addition to our Cobalt product line provides four channels of digital up conversion in a single module instead of four. This helps engineers save costs and greatly simplifies the design of synchronous beamforming radar and multichannel transceiver systems."
Channel independence in the Model 71670 is achieved with two new DAC3484 D/A converters from Texas Instruments (TI), each providing two digital upconverters (DUC) and 16-bit D/A channels with up to 16x interpolation that can translate a quadrature (I+Q) signal to a user-selectable IF center frequency.
"We began working with Pentek on their new D/A boards shortly after the DAC3484 became available," said Chuck Sanna, marketing manager for Texas Instruments' High Speed Products business. "With the DAC3484, Pentek was able to dramatically increase board density and performance thanks to the device's small package size and the industry's lowest power consumption."
The Model 71670's internal clock generator supports a wide range of timing modes and operates from an on-board programmable VCXO or an external clock. A front-panel connector accepts a 5 or 10 MHz reference clock to phase lock the internal programmable VCXO. The module also accepts a direct D/A sample clock input that can be as high as 1.25 GHz.
To offer precision timing control in a multi-module design, Pentek has implemented its new µSync timing bus in the Model 71670. The bus uses CML (current model logic) signaling for highest precision and includes clock, sync/reset, and gate/trigger signals that keep the operations of multiple modules sample-synchronized. Two modules can use the bus in a master/slave relationship to achieve 8-channel synchronization. For higher channel counts, the Model 7192 Cobalt Synchronizer can drive numerous modules using a star configuration.
The Model 71670 complies with the VITA 42.0 XMC interface specification, providing two gigabit serial connectors. The primary XMC connector supports x4 or x8 PCIe Gen 2 with multiple DMA controllers for efficient transfers to and from the module. The secondary connector supports two 4x or one 8x link with bit rates up to 3.125 GHz to support user-installed gigabit serial protocols such as Aurora, SRIO, or a secondary PCIe interface. An additional I/O option provides 20 LVDS differential pairs to the FPGA through the PMC P14 connector.
Like all Cobalt family modules, the Model 71670 includes a Xilinx Virtex-6 FPGA to implement internal data flow. The FPGA's factory-configured functions include a sophisticated Waveform Playback IP module that includes four linked list DMA controllers to support waveform generation from tables in either on-board or host memory. As many as 64 individual link entries are available for each channel and can be chained together to create complex waveforms with a minimum of programming.
Pentek also provides users with its GateFlow software development tool for implementing their own IP in the FPGA. The tool includes source code for the factory-implemented configuration as well as other system IP, allowing users to customize the module's default operation as well as incorporate their own proprietary IP. Customers can also choose the size of the FPGA on their module, ensuring they will have adequate capacity for implementing the functionality they desire.
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