Home > What's New > Upper Saddle River, NJ - October 27, 2008 |
"Building upon its Model 7150 hardware platform, Pentek has developed and installed full-function FPGA IP cores to create a series of turnkey solutions addressing a variety of applications. As the third member of this series, the 7153 extends both upper and lower ranges of signal bandwidths using a two- or four-channel DDC (digital downconverter) core," says Rodger Hosking, Vice President.
The Model 7153 DDC offers two modes of operation. The two-channel DDC mode sacrifices two DDC channels to boost the maximum decimation to 65,536 and extend the lower bandwidth limit down to 3 kHz. The four-channel DDC mode provides an independently programmable decimation range from two to 256 on each DDC, covering signal bandwidths from about 700 kHz to 90 MHz.
Switching between modes is invoked through firmware. In either mode, the user can independently select any one of the four A/Ds as the source for each DDC channel. With four A/Ds and four wideband DDCs, the Model 7153 is ideal for high-bandwidth radar and communication systems such as wideband CDMA, UMTS, SRW, LTE and 4G wireless.
In applications such as radar, direction finding and diversity receivers, it is essential to synchronize multiple channels, perform digital downconversion, control the gain and the phase delay of each channel and then perform a summation of the DDC outputs.
All of these critical beamforming facilities are included in the Model 7153. In addition to synchronous sampling and DDC for all four channels, the 7153 provides independent control of gain and phase for each DDC, and includes a summation block for the four DDC outputs.
For larger multichannel systems, multiple 7153s can be synchronized via the front panel LVPECL clock and sync bus. The DDC summation block includes high-speed serial links to the XMC connector for input and output ports. This supports daisy chain summation across multiple modules to greatly simplify beamforming applications with 8 or more antennas. Fully developed on-board IP and supplied firmware minimizes system integration efforts.
The Model 7153 has four embedded power meters that continuously monitor the average output power of each DDC channel. The power meters are readable by the system processor for measuring and detecting signal energy and for implementing AGC loops.
The power meters are capable of interrupting the system processor if the power level goes above or below programmable thresholds. Since the DDCs can be readily tuned across a frequency spectrum of interest, this feature simplifies critical signal-intelligence applications such as a radio scanner searching for energy.
In its native form, the Model 7153 is a PMC module. However, it is also available in PCI format for installation in a desktop PC or on an Intel-based blade server, and in 3U and 6U cPCI formats. It will soon be available for PCI Express systems.
Pentek supports the Model 7153 with its ReadyFlow board support libraries that are ported for Window, Linux and VxWorks.
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