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Model 4954-422 GateFlow IP Core Library - Wideband 280 MSPS DDC Core

This IP Core is no longer available for individual purchase. It is available installed in Pentek Model 6821.

Block Diagram




Life Cycle Management

Ordering & Warranty


  • IP Core only installed on Pentek FPGA board-level products
  • Ultra high-performance wideband digital downconverter (DDC)
  • Supports Virtex-II and Virtex-II Pro FPGAs
  • Fits in Virtex-II XC2V3000 or larger
  • Similar to the TI GC1012B with enhanced features
  • Dual demultiplexed inputs for 16-bit real or 16-bit complex (I and Q) data
  • Maximum input data rate of 280 MSPS
  • Maximum input bandwidth of 140 MHz (real inputs) or 280 MHz (complex inputs)
  • Fully programmable dual NCO with 32-bit frequency and phase offset control
  • NCO delivers > 110 dB SFDR
  • Decimation settings of 2, 4, 8, 16, 32, and 64 for complex output
  • Decimation settings of 1, 2, 4, 8, 16, and 32 for real output
  • Dual decimating FIR filter features up to 1792 taps
  • User-programmable 18-bit FIR filter coefficients
  • Default FIR filter coefficients for 80% and 90% filters
  • Output formatter delivers real, complex, offset, inverted data in 16 or 24 bits


Model 4954-422


Model 4954-422 Block Diagram

Please refer to the product datasheet for a larger version of the block diagram

Hardware and Software Manuals - ( top )

Please note that some hardware and software manuals are used for more than one Pentek product. Although the model numbers given in the description of each manual below may vary, these manuals are all used for the product described on this web page.

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