1
Pentek Homepage
Follow Us On LinkedIn Follow Us On Twitter Follow Us On YouTube Follow Us On Google Follow Us On Facebook Register AccountRegister Login AccountSign In
Board Selector   |  Recorder Selector   |  
Search:  
Home > Pipeline Newsletters > The Pentek Pipeline Vol. 27 No. 2
Pipeline Headline
Summer 2018 Vol. 27, No. 2
Quartz Zynq UltraScale+ RFSoC Family Products
Sign-Up for Quartz Zynq UltraScale+ RFSoC Updates!
Quartz Zynq UltraScale+ RFSoC Products Subscribe



Jade Kintex UltraScale FPGA Family
Sign-Up for Jade Kintex UltraScale Updates!
Jade Kintex UltraScale Products Subscribe



Cobalt Virtex-6 Products
Sign-Up for Cobalt Virtex-6 Updates!
Cobalt Virtex-6 Products Subscribe



Onyx Virtex-7 Products
Sign-Up for Onyx Virtex-7 Updates!
Onyx Virtex-7 Products Subscribe



Talon Recording Systems
Sign-Up for Talon System Updates!
Talon Recording Systems Subscribe



Flexor FMC Products
Sign-Up for Flexor FMC Updates!
Flexor FMC Products Subscribe



Pipeline Newsletter
Sign-Up for the Pipeline Newsletter!
Pipeline Newsletter Subscribe




Free Technical Resources:

Putting VPX and OpenVPX to Work Handbook
Putting VPX and OpenVPX
to Work Handbook

Download Now


High-Speed, Real-Time Recording Systems Handbook
High-Speed, Real-Time
Recording Systems Handbook

Download Now



High-Speed Switched Serial Fabrics Improve System Design Handbook
High-Speed Switched Serial
Fabrics Improve System Design

Download Now



Software Defined Radio Handbook
Software Defined Radio
Handbook

Download Now



Putting FPGAs to Work for Software Radio Handbook
Putting FPGAs to Work for
Software Radio Handbook

Download Now



Critical Techniques for High Speed A/D Converters in Real-Time Systems Handbook
Critical Techniques for High
Speed A/D Converters in
Real-Time Systems Handbook

Download Now




Pentek Literature:

Analog and Digital I/O Catalog
Analog & Digital I/O Catalog
Clock and Sync Generators Catalog
Clock & Sync Generators Catalog
Radar and SDR I/O Catalog
Radar & SDR I/O Catalog
Software and FPGA Tools Catalog
Software & FPGA Tools Catalog
High-Speed Recording Systems
High-Speed Recording Systems
Pentek Product Catalog
Pentek Product Catalog
Jade Xilinx Kintex UltraScale FPGA Family
Jade FPGA Family
Onyx Virtex-7 and Cobalt Virtex-6 FPGA Family
Onyx & Cobalt FPGA Family
Product Overview
Product Overview
Company Profile
Company Profile




Request Free Technical Literature



Download the PDF Version of the Pentek Pipeline Newsletter

Strategies for Deploying Xilinx's Zync UltraScale+ RFSoC

by Bob Sgandurra

On February 21st, 2017, Xilinx® announced the introduction of a new technology called RFSoC with the rather dramatic headline "Xilinx Unveils Disruptive Integration and Architectural Breakthrough for 5G Wireless with RF-Class Analog Technology." The proposition was simple: add RF-class analog to digital and digital to analog data converters to Xilinx's already powerful MPSoC, ARM processor enhanced family of high performance FPGAs.

Strategies for Deploying Xilinx's Zync UltraScale+ RFSoC

And while the concept was simple, the implications were profound, changing the way engineers could design and package small, high channel count systems. And this technology not only offers new possibilities for 5G applications, but has significant impact in military and scientific systems, justifying the claim in Xilinx's announcement. To get better appreciation of the capabilities of RFSoC and understand how to best use the advantages of this technology, it's worth taking a quick look at current trends in data converters and signal processing.



Product Focus

8 Channel A/D and D/A Zynq UltraScale+ RFSoC Processor

Features

  • Supports Xilinx Zynq UltraScale+ RFSoC FPGAs
  • 18 GB of DDR4 SDRAM
  • On-board GPS receiver
  • PCI Express (Gen. 1, 2 and 3) interface up to x8
  • LVDS connections to the Zynq UltraScale+ FPGA for custom I/O
  • Optional VITA-66.4 optical interface for backplane gigabit serial communication
  • Dual 100 GigE UDP interface
  • Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4, VITA-57.4 and VITA-65 (OpenVPX™ System Specification)
  • Ruggedized and conduction-cooled versions available
Model 5950
Model RTR 5950

Quartz family of Xilinx Zynq UltraScale+ RFSoC FPGAs



Product Focus

2-Channel 200 MHz A/D with 766 DDCs, Kintex UltraScale FPGA

Features

Model 71865
Model 71865

Jade Kintex UltraScale FPGA Family



Product Focus

Kintex UltraScale FPGA Coprocessor

Features

Model 71800
Model 71800

Jade Kintex UltraScale FPGA Family



With Pentek's New Jade Architecture Came a New Documentation Architecture

What has changed?
  • Documentation is HTML-based and can be viewed from any web browser. This new format started with the Jade family of products and will be used with Quartz and all future products.
  • This new format allows easier access to the complete product documentation set (hardware, software, and IP), with all manuals linked and accessible through the same interface. A powerful search feature helps users quickly find the information they need.
  • The documentation is delivered on DVD, with updates available via our FTP site, so it does not require an internet connection.
Why the change?

The AXI4* implementation in the Jade architecture distributes control registers throughout the block diagrams, which is different from a centralized control register memory map. Because of this, the address information must be navigated in a different way than in the past and using an HTML, linkable format puts the register information right at your fingertips.

*AXI4 is the fourth generation of an interface specification from ARM® commonly used in the semiconductor industry. Xilinx has adopted this standard to create AXI4-compliant plug-and-play IP. Navigator FDK follows the AXI4 standard. For Pentek's Jade products, the FDK includes the complete IP that is factory-installed in the board.

This includes all interface, processing, data formatting, DMA functions, etc. IP designers can modify or replace functions as needed to match application requirements, and will find immediate compatibility with Xilinx IP and third-party IP that uses AXI4. Designers who create their own custom IP using the AXI4 standard will find integration with the Pentek-supplied IP straightforward.


How is it organized?

The picture below shows the user manual library for Jade Model 78851. To the left, the table of contents panel lists the HTML manuals: Getting Started, Installation, and Operation. The center of the screen provides easy access to block diagrams, memory maps, the interrupt tree, and the Navigator BSP software manual.

Documentation is HTML-based

How do I get it?

Each Jade product is shipped with a DVD containing its user manual library. If you sign up to receive product update notifications via YourPentek, when the library is updated, you'll get an email notification. Clicking on the link in the email will download a short document that describes the user manual library and tells you what has been updated in it (to see an example, click here). The document also contains instructions for how to download a zip file that contains the updated library.

We are excited about this new format for our documentation because we believe it will better serve our customers.

Pipeline Newsletter Footer



CONNECT ON SOCIAL:  Follow Us On Facebook Follow Us On LinkedIn Follow Us On Twitter Follow Us On Google+ Follow Us On YouTube

Pentek, Inc. • One Park Way, Upper Saddle River, NJ, 07458, USA
Tel: +1 (201) 818-5900 • Fax: +1 (201) 818-5904 • Map + Directions • Site Map
Terms Of Use • Privacy Policy • Copyright © 2018 Pentek, Inc. All Rights Reserved.