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Home > What's New > Models 7742 / 7742D Multichannel Transceiver with Virtex-4 FPGAs - PCIe

Spring 2009 Vol. 18, No. 1

Models 7742 / 7742D Multichannel Transceiver with Virtex-4 FPGAs - PCIe


  • Four or eight 125 MHz, 14-bit A/Ds; one or two 500 MHz, 16-bit D/As
  • One or two DUCs (upconverters)
  • Up to 1.5 GB of DDR SDRAM
  • Two or four Xilinx Virtex-4 FPGAs
  • Input signal bandwidths to 50 MHz
  • Sample clock synchronization to an external system reference
  • LVDS clock/sync bus for multiboard synchronization
  • Optional installed IP cores available
  • Complete software radio interface solution

General Information

Model 7742 is a multichannel data converter suitable for connection to HF or IF ports of a communications system. It includes four A/Ds with one upconverter and D/A converter (Model 7742), or eight A/Ds with two upconverters and D/As (Model 7742D). It attaches to motherboards with full-length PCIe (PCI Express) interface slots for installation in various PCs, blade servers and computer systems.

A/D Converter Stage

The front end accepts four or eight fullscale analog HF or IF transformer-coupled inputs on front panel MMCX connectors at +10 dBm into 50 ohms into Linear Technology LTC2255 14-bit 125 MHz A/Ds. The digital outputs are delivered into a Virtex-4 FPGA for signal processing or for routing to other module resources.

Digital Upconverter and D/A

The 7742 features one or two TI DAC5686 DUCs with D/As. Each accepts a baseband real or complex data stream from its attached FPGA with signal bandwidths up to 40 MHz.

When operating as an upconverter, the DAC5686 interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 160 MHz. It delivers real or quadrature (I+Q) analog outputs up to 320 MHz to the 16-bit D/A converter. If translation is disabled, the DAC5686 acts as an interpolating 16-bit D/A with output sampling rates up to 500 MHz.

Virtex-4 FPGAs

The 7742 architecture includes two or four Virtex-4 FPGAs. All of the board's data and control paths are accessible by the FPGAs, enabling installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition, users can include their own custom IP and integrate it with factory-shipped functions using GateFlow® FPGA Design Resources.

Memory Resources

Three independent 256 MB banks of DDR2 SDRAM are available to each SX55 or LX100 FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and a D/A waveform generator mode. All memory banks can be easily accessed through the PCI interface.

PCI Express Interface

The 7742 includes a multiple port, 48-lane Gen 2 PCIe switch with integrated SerDes. The switch provides 16X wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with two optional 4X PCIe connections to each SX55/LX100 FPGA, and one 4X connection to each 64-bit PCI interface.

For more information and price quotation on the Model 7742, click here or on the Model 7742D, click here.

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