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Home > Pipeline Vol. 17 No. 2 > Product Focus: Model 7141-430

Summer 2008 Vol. 17, No. 2

Model 7141-430 Transceiver with 256-Channel Narrowband DDC Installed Core


  • Installed Core 430 with 256 channels of narrowband DDCs installed
  • 256 fully programmable NCOs with 32-bit frequency tuning resolution
  • Programmable decimation settings from 1024 to 9984 in steps of 256
  • Two 125 MHz A/Ds and two 500 MHz D/As included
  • LVDS clock/sync bus for multimodule synchronization
  • Also available in PCI and cPCI formats

GateFlow FPGA Design Resources

General Information

Model 7141-430, Dual Digital Transceiver with 256-Channel Narrowband DDC Core 430, is a complete software radio system in a PMC/XMC module. It includes two A/D and two D/A converters for connection to HF or IF ports of a communications or radar system.

The 7141-430 receiver section features two LTC2255 125 MHz 14-bit A/D converters and one Texas Instruments GC4016 quad multiband digital downconverter. The GC4016 supports a decimation range from 32 to 16,384. For an A/D sample clock frequency of 100 MHz, the output bandwidth for each of the four channel ranges from 2.5 MHz down to 5 kHz. By combining two or four channels, decimations of 16 or 8 can be achieved for an output bandwidth of up to 5 or 10 MHz, respectively.

For applications that require many channels of narrowband downconverters, Pentek offers the installed IP Core 430 256-Channel Digital Downconverter bank. Factory installed in the 7141-430 FPGA, Core 430 creates a flexible, very high channel count receiver system in a small footprint.

Core 430: 256-Channel DDC Bank

Unlike legacy channelizer methods, the Pentek 430 core allows for independent programmable tuning of each channel with 32-bit resolution. Filter characteristics are comparable to many conventional ASIC DDCs.

Added flexibility comes from programmable global decimation settings ranging from 1024 to 9984 in steps of 256, and 18-bit user programmable FIR decimating filter coefficients for the DDCs. Default DDC filter coefficient sets are included with the core for all possible decimation settings.

Core 430 utilizes a unique method of channelization. It differs from others in that the channel center frequencies need not be at fixed intervals, and are independently programmable to any value.

Flexible Architecture

Core 430 DDC comes installed in the Model 7141-430. A multiplexer in front of the core allows data to be sourced from either A/D converter, A or B. At the output, a multiplexer allows for routing either the output of the GC4016 or the Core 430 DDC to the PCI Bus.

In addition to the DDC outputs, data from both A/D channels are presented to the PCI Bus at a rate equal to the A/D clock rate divided by any interger value between 1 and 4096. A Texas Instruments DAC5686 digital upconverter and dual D/A accepts baseband real or complex data streams from the PCI Bus with signal bandwidths up to 50 MHz. The analog outputs are transformer-coupled to front panel MMCX connectors.

Clocking and Synchronization

Two independent internal timing buses can provide either a single clock or two different clock rates for the input and output signals. Each timing bus includes a clock, a sync, and a gate or trigger signal. Signals from either timing bus A or B can be selected as the timing source for the A/Ds, the downconverter, the upconverter and the D/As.

Performance characteristics are included at the end of this issue. For more information and price quotations on the Model 7141-430 commercial and rugged versions, go to: click here.


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