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Home > Pipeline Vol. 17 No. 1 > Product Focus: Model 7151

Spring 2008 Vol. 17, No. 1

Model 7151 256-Channel Digital Downconverter with Quad 200 MHz, 16-bit A/D PMC Module


  • 256 channels of DDC
  • Four 200 MHz 16-bit A/Ds
  • DDC decimation from 128 to 1024 in steps of 64
  • Common decimation factor within each DDC bank
  • Different decimation factors between banks
  • Each bank independently selects one of four A/Ds
  • User-programmable 18-bit FIR filter coefficients
  • Default filters offer 0.2 dB ripple and 100 dB rejection
  • LVDS clock/sync bus for multi-module synchronization

General Information

Model 7151 is a 4-channel, high-speed digitizer designed for processing baseband RF signals or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a high-performance 256-channel installed DDC (digital downconverter) IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems.

Model 7151 uses the industry standard PMC daughtercard format compatible with numerous carrier boards for VME, PCI, and CompactPCI.

A/D Converter Stage

The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +10 dBm into 50 ohms with transformer coupling to four 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

DDC Input Selection and Tuning

The Model 7151 employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank.

Each of the 256 DDCs has an independent 31-bit tuning frequency setting that ranges from DC to ƒs/2, where ƒs is the A/D sample rate.

Decimation and Filtering

All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 190 MHz, the available output bandwidths range from 148.4 kHz to 1.2 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board.

The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒs/N, where N is the decimation setting. The rejection of adjacentband components within the 80% output bandwidth is better than 100 dB.

Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of ƒs/N. Any number of channels can be enabled with each bank, selectable from 0 to 64. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

Output Multiplexers and FIFOs

Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application.

Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.


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