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Home > Pipeline Vol. 16 No. 3 > Tools for Real-Time Embedded System Development

Fall 2007 Vol. 16 No. 3   


Model 7142-428 Transceiver with Four Multiband DDCs and Interpolation Filter - PMC/XMC


  • Complete software radio transceiver solution
  • Four 125 MHz 14-bit A/Ds
  • Two Xilinx Virtex-4 FPGAs
  • One 500 MHz 16-bit D/A
  • Installed Core 428 with four high performance multiband DDCs and Interpolation Filter installed
  • Two sets of 18-bit user-programmable FIR filter coefficients
  • Decimation range from 2 to 65,536
  • Interpolation range from 2 to 32,768
  • I/O bandwidths from 8 kHz to 40 MHz
  • Multiple module synchronization

Model 7142-428 Installed Core

General Information

Model 7142-428, Digital Transceiver with Multiband DDC Core and Interpolation Filter, is a complete software radio system in a PMC/XMC module. It includes four A/D and one D/A converters capable of bandwidths to 40 MHz and above for connection to HF or IF ports of a communications or radar system.

The front end accepts four full scale analog HF or IF inputs on front panel MMCX connectors at +10 dBm into 50 ohms with transformer coupling into Linear Technology LTC2255 14-bit 125 MHz A/D converters.

The digital outputs are delivered to the Virtex-4 FPGA for signal processing or for routing to other module resources.

A TI DAC5686 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA with signal bandwidths up to 40 MHz.

When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 160 MHz. It delivers real or quadrature (I+Q) analog output samples at up to 320 MHz to the 16-bit D/A converter. Analog output is through a front panel MMCX connector at +4 dBm into 50 ohms. If translation is disabled, the DAC5686 acts as an interpolating 16-bit D/A with output sampling rates up to 500 MHz.

Core 428 Multiband DDCs

The Core 428 downconverter translates any frequency band within the input bandwidth range down to zero frequency. The DDCs consist of two cascaded decimating FIR filters. Each filter is capable of any decimation from 2 to 256. The decimations of the first stage filter and the second stage filter multiply to yield overall decimation factors up to 65,536.

The NCO provides over 108 dB spurious-free dynamic range (SFDR). The FIR filter is capable of storing and utilizing two independent sets of user-programmable 18-bit coefficients.

Four identical Core 428 DDCs are factory installed in the 7142 FPGA. An input multiplexer allows any DDC to independently select any of the four A/D sources. The total decimation range from 2 to 65,536 provides output bandwidths from 50 MHz down to 1.52 kHz for an A/D sampling rate of 125 MHz and assuming an 80% filter.

Core 428 Interpolation Filter

The Core 428 interpolation filter increases the sampling rate of real or complex baseband signals by a factor of 16 to 2048, programmable in steps of 4, and relieves the host processor from performing upsampling tasks. The interpolation filter can be used in series with the DUC's built-in interpolation, creating an interpolation factor up to 32,768.

For more information and a price quotation, click here.



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