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Home > Pipeline Vol. 15 No. 3 > Model 7142 PMC/XMC Multichannel Transceiver Boosts FPGA, Memory and A/D

Fall 2006 Vol. 15 No. 3   


The Model 7142 PMC/XMC module provides complete software radio transceiver functions suitable for IF or RF communication systems and offers increased capabilities. These include dual Virtex-4 FPGAs, four A/D converters, an upconverter with D/A and large SDRAM memory.

The Model 7142 is also available in a variety of form factors including PCI (Model 7642), 6U and 3U cPCI (Models 7242 and 7342), as well as rugged and conduction-cooled versions.

A/D Converters

The front end accepts four full scale analog HF or IF inputs at +4 dBm into 50 ohms with transformer coupling into Linear Technology 14-bit 125 MHz A/D converters.

The digital outputs are delivered into the Virtex-4 FPGA for signal processing or for routing to other module resources.

Upconverter and D/A Converter

A TI DAC5686 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA with signal bandwidths up to 40 MHz.

When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 160 MHz. It delivers real or quadrature (I+Q) analog outputs at up to 320 MHz to the 16-bit D/A converter. Analog output is at +4 dBm into 50 ohms.

If translation is disabled, the DAC5686 acts as an interpolating 16-bit D/A with output sampling rates up to 500 MHz.

Virtex-4 FPGAs

The Model 7142 architecture includes two Virtex-4 FPGAs. All of the board's data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control.

The Xilinx XC4VSX55 features 512 DSP slices and is ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission.

For applications requiring more FPGA logic cells, the Model 7142 can be optionally configured with an XC4VLX100 in place of the XC2VSX55 for 110,592 logic cells.

A second Virtex-4 FPGA provides board interfaces including PCI and serial I/O. The XC4VFX60 FPGA also includes two PowerPC cores which can be used as local microcontrollers to create complete application engines.

Clocking and Synchronization

Two independent internal timing buses can provide either a single clock or two different clock rates for the input and output signal paths. Each timing bus includes a clock, a sync, and a gate or trigger signal. Signals from either Timing Bus A or B can be selected as the timing source for the A/Ds and the upconverter and the D/A. Two internal crystal oscillators and a front panel reference input or LVDS bus can drive the timing buses.

A front panel 26-pin LVDS Clock/Sync connector allows multiple modules to be synchronized.

Memory Resources

Three independent 256 MB banks of DDR2 SDRAM are available to the FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and a D/A waveform generator mode. All memory banks can be easily read or written to through the PCI interface. For more information on the Model 7142 Multichannel Transceiver, click here.

See Model 7142 Datasheet for larger block diagram.



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