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Upper Saddle River, NJ - March 31, 2014 - Pentek, Inc., today announced the newest member of its highly popular Onyx® family of high-speed data converter XMC FPGA modules: the Onyx Model 71741, a 1-channel, 3.6 GHz 12-bit A/D or 2-channel, 1.8 GHz 12-bit A/D XMC module based on the high density Xilinx Virtex-7 FPGA. The Model 71741 can digitize signal bandwidths up to 1500 MHz.
The front end accepts analog RF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz or in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. A built-in AutoSync feature supports A/D synchronization across multiple modules.
A powerful DDC intellectual property (IP) core sets the Model 71741 apart from the competition. The DDC supports a single-channel mode, accepting data samples from the A/D converter at the full 3.6 GHz rate. It also operates as a dual channel DDC when the A/D is set for 2-channel 1.8 GHz operation. Each DDC accepts an independent 32-bit tuning frequency setting that ranges from DC to the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x.
The Model 71741 comes preconfigured with a suite of built-in functions for data capture, synchronization, time tagging and formatting, making the board an ideal turn-key interface for radar, communications or general data acquisition applications. The Model 71741 features an A/D acquisition IP module for easy capture and data moving.
These IP modules greatly enhance the functionality of the Model 71741 and reduce the development time and effort to module deployment. "The Model 71741, with its built-in DDC IP core, can eliminate costly digital and analog RF front-ends for the down conversion," said Bob Sgandurra, Pentek's director of Product Management. "The increased space for IP in the Virtex-7 also leaves plenty of additional room for customer supplied applications."
As compared to the proven design in the Cobalt Virtex-6 family, architectural enhancements in the Onyx family include a doubling of the DDR3 memory in both size and speed to 4 GB and 1600 MHz, respectively. The PCIe interface has been upgraded to Gen 3, delivering peak transfer rates up to 8 GB/sec. The Virtex-7 is more power efficient than previous generations making it easier to utilize larger FPGAs. Optional LVDS and gigabit serial connections to the Virtex-7 are available for connecting to custom high performance I/O.
GateXpress® PCIe Configuration Manager is a sophisticated FPGA-PCIe hardware engine for managing FPGA reconfiguration. At power up, the GateXpress manager immediately presents a PCIe target to the host computer for discovery and enumeration, giving the FPGA time to load from FLASH. Once booted, the GateXpress manager offers multiple options for dynamically reconfiguring the FPGA with a new IP image, handling the hardware negotiation and streamlining the loading task. GateXpress also allows dynamic FPGA reconfiguration though software commands as part of the runtime application.
For systems that require custom functions, IP can be developed using the Pentek GateFlow® FPGA Design Kit, extending or even replacing the factory-installed functions. Software support packages are available for Linux and Windows operating systems.
The Model 71741 XMC module is designed for both rugged and COTS environments and is available in cPCI (Model 73741 and Model 72741), AMC (Model 56741), PCIe (Model 78741) and VPX (Model 52741 and Model 53741).
For the latest pricing, delivery and available options, please fill out this form and your request will be delivered to the appropriate department. To learn more about our products or to discuss your specific application please email our sales department at email@example.com, contact your local representative or Pentek directly:
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