Pentek's Digital Receiver Board with High-Speed A/D and Installed FPGA Dual-Channel Digital Downconverter Eliminates FPGA Development Tasks
- High-speed A/D with 12-bit sample rate at 215 MHz
- GateFlow wideband digital downconverter FPGA IP Core
- Preconfigured combination software radio subsystem, fully tested
- Powerful data-acquisition front end for DSP and recording systems
- Four sets of user-programmable FIR coefficients for custom filtering
- Ruggedized and conduction-cooled versions
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Pentek, Inc., the industry pioneer of board- and system-level technology, today released the newest member of its popular GateFlow installed-core products, Model 6821-422. Based on the popular Model 6821 215 MHz A/D Converter VME with dual Virtex-II Pro FPGAs, it includes a factory-installed wideband digital downconverter (DDC) IP core. This DDC is a highly optimized dual-channel version of Pentek's GateFlow IP Core 422 tailored precisely to the various resources of the board.
The result is a complete, preconfigured digital software radio subsystem that accepts a front-panel analog RF input and delivers real or complex digital output samples translated to baseband from any frequency slice of the input signal.
Applications particularly well suited for Model 6821-422 include wideband recording and systems, real-time DSP and software radio systems, and data-acquisition applications for wideband communication signals used in telemetry and SATCOM. Radar-pulse and beamforming applications especially benefit from the board's many gate, trigger and multi-channel synchronization modes.
'This product is the latest in our family of preconfigured and fully tested subsystems for customers who want to take advantage of advanced FPGA signal processing right out of the box. They get supercharged hardware without having to do any FPGA development,' commented Pentek vice president Rodger Hosking. 'This is extremely attractive to customers who want to avoid the risks and schedule slips often caused by custom FPGA design efforts. Customers can buy the core already installed, delivered quickly and working at a well defined functional level with virtually zero risk,' Hosking added.
IP Core Compared to ASIC Counterpart
By using a unique polyphase implementation, the FPGA IP Core 422 leapfrogs the commonly used TI/Graychip GC1012B ASIC in speed, dynamic range and programmability. The core operates at frequencies up to 296 MHz, while most ASIC downconverters top out near 150 MHz. In addition, the 422 Core uses higher-precision math than ASIC devices to deliver adjacent channel rejection of up to 100 dB and frequency tuning resolution of 32 bits. Instead of a single fixed low-pass filter, the 422 core offers four sets of programmable coefficients stored in user-accessible RAM. These coefficients are preloaded with 80 percent and 90 percent filters during power-up, but can be overwritten during runtime for custom filter characteristics.
Architecture: Inside the 6821-422
An Analog Devices AD9430 A/D converter digitizes the incoming signal at 215 MHz and delivers identical sample streams of two independent 422 DDC cores, one in each of the XC2VP50 FPGAs. Within each core, an input stage allows scaling of the A/D samples by a 16-bit gain term. Even and odd samples are split into two streams that are directed into two DDC engines operating in parallel. A direct digital frequency synthesizer (NCO) core generates the desired center frequency of the band of interest. It delivers two complex local oscillator signals, offset slightly in phase, to two complex digital mixers that perform frequency translation of the input signal to 0 Hz. Dual FIR low-pass filters limit the output bandwidth and a final combining, decimation and formatting stage delivers real or complex output samples as required. The filters can use one of four independent sets of 18-bit coefficients for each of the six decimation settings. The cores also offer a bypass mode that routes the digital samples straight to the output with a simple software switch.
The digital output signals are available on two or four front panel data port (FPDP) connectors using several data-packing modes. In addition, the signals can be delivered as low voltage differential signaling (LVDS) through either the VMEbus P2 connector or a second-slot front-panel mezzanine.
Software Support
The Model 6821-422 is supported by Pentek's C-callable ReadyFlow Board Support Libraries. ReadyFlow provides development tools for quick startup through application completion, allows programming at high, intermediate and low levels to meet various needs, and includes complete source code for all functions.
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