Upper Saddle River, NJ - September 25, 2012 - Pentek, Inc., today released its highest-performing D/A converter module for RF and IF waveform playback, the Cobalt® Model 71671. The module delivers four independent analog outputs each through its own digital upconverter and 16-bit D/A with sampling rates to 1.25 GHz. An on-board Xilinx Virtex-6 FPGA contains factory-installed IP that provides turnkey waveform generation for output signal bandwidths from less than 1 kHz up to 250 MHz with an extended interpolation range from 2x to 1,048,576x. Users can also customize the module's operation by implementing their own IP in the FPGA.
The Model 71671 uses two DAC3484 D/A converters from Texas Instruments (TI), each providing two digital upconverters (DUCs) and 16-bit D/A channels that can translate a quadrature (I+Q) baseband signal to a user-selectable IF center frequency for transmitting.
Complementary synchronizer products can deliver clock and timing signals to multiple 71671 modules for synchronizing, triggering and gating functions. Synchronization is essential for multichannel applications like phased array radars and beamformed communications antennas. These applications abound in government and military systems, but the same beamforming concepts are also used in medical and industrial systems.
"The built-in IP for extended interpolation allows customers to handle an extremely wide range of transmit signal bandwidths," noted Rodger Hosking, vice president of Pentek. "Because the DAC3484 provides a maximum interpolation of only 16x, it accommodates input transmit signal bandwidths from 250 MHz down to 62.5 MHz. However, many radar and communication signals need to generate IF signals with much lower bandwidths. By extending the interpolation to 1,048,576x, the Model 71671 now supports input signal bandwidths as low as 850 Hz while still covering maximum bandwidths up to 250 MHz, making it a perfect complement to our family of Cobalt A/D converter modules with built-in digital downconverters."
The Model 71671's internal clock generator supports a wide range of timing modes, and operates from an on-board programmable VCXO or an external clock. A front-panel connector accepts a 5 or 10 MHz reference clock to phase lock the internal programmable VCXO. The module also accepts a direct D/A sample clock input.
To offer precision timing control in a multi-module design, Pentek has implemented its new µSync timing bus in the Model 71671. The bus uses CML signaling for highest precision and includes clock, sync/reset, and gate/trigger signals that keep the operations of multiple modules sample-synchronized. The Model 7192 and Model 9192 Synchronizer can drive up to 12 modules.
The Model 71671 complies with the VITA 42.0 XMC interface specification, providing two gigabit serial connectors. The primary XMC connector supports x4 or x8 PCIe Gen 2 with multiple DMA controllers for efficient transfers to and from the module. The secondary connector supports two 4x or one 8x link with bit rates up to 3.125 GHz to support user-installed gigabit serial protocols such as Aurora, SRIO, or a secondary PCIe interface. An additional I/O option provides 20 LVDS differential pairs to the FPGA through the PMC P14 connector.
Like all Cobalt family modules, the Model 71671 includes a Xilinx Virtex-6 FPGA to implement internal data flow. The FPGAs factory-configured functions include a sophisticated Waveform Playback IP module with four linked-list DMA controllers to support waveform generation from tables in either on-board or host memory. Up to 64 individual link entries are available for each channel, and they can be chained together to create complex waveforms with a minimum of programming.
Pentek also provides users with its GateFlow® software development tool for implementing custom IP in the FPGA. The tool includes source code for the factory-implemented configuration as well as other system IP, allowing users to customize the module's default operation as well as incorporate proprietary IP. Customers can also choose the size of the FPGA on their module, ensuring they will have adequate capacity for implementing the functionality they desire.
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