New technologies offer engineers of SDR (software-defined radio) systems diverse opportunities to perform digital-signal processing much closer to the antenna than ever before. Strategies for doing so include the latest wideband data converters, monolithic receiver chips, compact RF tuners, and remote receiver modules using gigabit serial interfaces. Each approach presents benefits and tradeoffs that must be considered in choosing the optimal solution for a given application.
With the emergence of monolithic A/D converters capable of sampling rates of 5 GHz and higher, engineers can now directly digitize analog RF signals covering a frequency span of more than 2 GHz. This allows the capture of wideband communications and radar signals in a single data stream, eliminating the complexity of splitting a given band into parallel adjacent sub-bands and the inevitability of input signals straddling them. While these new converters appear to simplify software radio architectures, they also impose many limitations and tradeoffs.
RF signals from the antenna must first be amplified, filtered and possibly downconverted in frequency to match the input voltage range and usable input bandwidth of the A/D converter. Optimal amplifier gain boosts the strongest signal to the full scale input range of the A/D. Further amplification to boost weaker in-band signals will cause overloading of the A/D, which destroys the signal integrity for all signals. Thus, even one strong interfering signal will reduce the achievable dynamic range for weaker signals. This significant tradeoff occurs whenever a single A/D is used to handle a large number of signal types in a wide frequency span.
To make matters worse, as sampling rates increase, A/D converters deliver lower ENOB (effective number of bits) ratings. For example, a 5 GS/sec 10-bit A/D converter may only deliver an ENOB of 7.6 bits.
In addition, filtering is imperative to eliminate all energy outside the frequency span of interest. Otherwise, aliasing will fold out-of-band noise and adjacent signals into the digitized signal stream, degrading signal-to-noise performance and creating spurious signals.
Lastly, A/D data arriving at several gigasamples per second will overload most digital signal processors. Data de-interleaving hardware is often built into the A/D to help implementation of the electrical interface, but even so, every data sample must somehow be processed, stored or transferred. The latest families of FPGAs are especially well suited, not only in dealing with these extremely high data interface rates, but also in processing signals in real time.
A typical product example, the Pentek Model 53641 3.6 GHz A/D and DDC ruggedized OpenVPX board, is shown in Figure 1. It features a 12-bit 3.6 GS/sec A/D converter coupled to a Virtex-6 FPGA. The A/D deinterleaves samples into eight parallel 12-bit streams, delivering samples to the LVDS ports of the FPGA at 450 MS/sec each.
Inside, eight parallel engines implement a DDC (digital downconverter) that tunes across the 1.8 GHz input band. It performs frequency translation to baseband and provides digital filtering of the complex baseband output samples. Selectable output bandwidths of 90, 180 or 360 MHz, representing tunable slices of the input spectrum, are delivered to the system through a native PCIe Gen. 2 x8 interface.
New classes of monolithic silicon receivers offer an impressive integration of diverse RF analog circuitry required to implement a complete software radio tuner front end. These low-cost devices accept input signals directly from the antenna and deliver amplified, translated and filtered analog baseband outputs suitable for low-speed A/D converters or demodulator chips.
For example, the Maxim MAX2112, used in the Pentek Model 78690 PCI Express board shown in Figure 2, targets satellite set-top and VSAT applications including 8-PSK modulation and Digital Video Broadcast (DVB-S2) applications. It uses an LNA to boost antenna input signals falling between 925 and 2175 MHz, as well as a programmable-gain RF amplifier for 60 dB of overall gain control.
An integrated VCO and programmable fractional-N frequency synthesizer drive a quadrature mixer to tune across the entire input frequency range, downconverting any input signal to I+Q baseband. These baseband signals are band-limited with a pair of low- pass filters, programmable from 4 to 40 MHz.
The analog baseband I and Q tuner outputs are then applied to two Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.
This extremely high level of integration on a single PCIe board reduces the size and cost of the receiver, and is ideal for applications restricted in space, power, weight and cost, or requiring a large number of channels.
However, while these devices work well for applications requiring only modest signal-to-noise ratios like satellite signal interception, they are not suitable for some of the more demanding government and military systems for communications, signals intelligence and radar.
These higher dynamic range requirements require better RF analog signal processing, including multi-conversion designs, amplifiers with lower noise figures, local oscillators with better phase noise and wider tuning ranges, mixers that minimize unwanted spurs, and filters with better pass-band flatness, roll off and stop-band performance. Other critical factors include packaging, shielding, isolation, voltage regulation, vibration tolerance and thermal performance.
Boosting overall performance of the system is achieved by progressively improving the weakest of these signal chain elements in iterative cycles until the desired result is reached.
Each level of improvement leads directly to system level performance benefits such as lower bit error rates for digital communication systems, improved target detection range and classification accuracy for radar systems, higher intelligibility of voice interceptors, and the enhanced precision of target location and trajectory for weapons control systems.
As a result, there is a continuum of required software radio performance levels matching the operational objectives and constraints of a wide range of systems. At the low end, the monolithic receiver described above may suffice, while a very sensitive SIGINT receiver might require a large, highly-sophisticated RF subsystem.
As another factor, many applications need to cover only a limited range of input signal frequencies, such as an upper-band GSM receiver handling signals between 1700 and 2000 MHz. For these band-limited systems, simpler single-conversion RF tuner architectures can still deliver good performance. In these systems a single local oscillator and mixer downconvert the RF signal to a lower frequency IF signal compatible with a high-resolution A/D converter. Of course, judicious selection of amplifiers and filters, and careful analysis and suppression of mixer products are essential design tasks.
Because of the narrow tuning range, these types of RF tuners are often called "slot receivers". They can be ideal for dedicated applications where limited frequency coverage, cost, size and weight allow placement of the tuner at or near the antenna.
One illustrative example is the Pentek Model 8111 RF Slot Receiver shown in Figure 3. An input band-pass filter rejects signals outside the defined RF tuning "slot", helping to eliminate both out-of-band noise and discrete interfering signals. The mixer and tunable local oscillator translate the RF input down to an IF frequency of 225 MHz. An IF bandpass filter excludes all signals outside an 80 MHz band centered at 225 MHz, delivering an analog output suitable for 14- or 16-bit A/D converters.
Low-noise amplifiers and programmable attenuators in the signal chain boost antenna signal levels to match the full-scale input voltage of the A/D. Pentek offers seven different models, each covering a different 400 MHz slot between 800 MHz and 3 GHz. An overlap of 100 MHz between adjacent slots ensures that any 80 MHz signal band can be accommodated.
Delivering high-frequency RF signals through long coaxial cables from the antenna to the receiver system has several disadvantages. First, the higher the frequency, the more signal loss in the cable. To mitigate this, LNBs (low noise blocks) located on the antenna are commonly used to downconvert signals above 4 GHz (C-band and higher) to a lower frequency typically often in the L-band (1-2 GHz). Nevertheless, cables carrying these analog signals still suffer degradation and present EMI radiation and susceptibility issues. Not only do they impose a tangible weight impact in aircraft and UAVs, they also become maintenance burdens for the extremely long runs and the salt environment aboard ships.
The techniques discussed above present receiver system engineers new opportunities for digitizing signals right at the antenna. The proliferation of industry standard gigabit serial digital links offers many benefits in transmission and distribution of these digitized receiver signals. For example, GbE and 10 GbE links are so widely deployed in computer networks, WAN and LAN servers and data processing centers that commercial competition has driven down costs of components, switches, bridges, cables and other infrastructure.
In the embedded computing market, FPGA vendors not only offer built-in PCIe ports, they also offer native light-weight gigabit serial protocols such as Xilinx’s Aurora and Altera’s SerialLite. These, along with SerialFPDP, are ideal for delivering raw A/D or baseband I+Q samples from an FPGA-based front end. At the receiving end, host bus adapters are available for all of these protocols, and many embedded systems processors have native interfaces for SerialRapidIO and PCIe.
Each of these gigabit serial links can be delivered over copper or optical cables. Single-mode fibre cables can connect data from remote receivers up to 10 km away. This benefits large antenna array installations that must collect signals from a grid of widely spaced antennas. Optical cables are free from EMI radiation, eliminating interference to other electronics in tightlypacked manned and unmanned aircraft as well as offering security against eavesdropping. They are also immune to EMI pickup from powerful transmitters, motors and generators found in ship borne installations. Lastly, optical cables are much lighter than copper cables and are highly resistant to moisture, salt and chemicals.
There is no substitute for appropriate analog RF signal conditioning prior to A/D conversion, and each technique presents its own application-specific tradeoffs. Nevertheless, the added benefits of antenna site software radio receivers are numerous.
FPGAs can implement essential DDC functions and deliver digital baseband samples across an industry-standard digital gigabit serial link. Because these links are full-duplex, the same cable provides a path for control and status functions for the host. Digital receiver data can be easily distributed to multiple destinations using low cost switches and readily archived on storage servers, as shown in Figure 4.
For sensitive signals and classified information, data encryption can be easily included before transmission. Additional preprocessing algorithms such as radar pulse-compression, FFT energy calculations, scanning and threshold detection can be incorporated within the FPGA to reduce transmission data rates and offload these processing tasks from the host system.
It is apparent that many applications can benefit from pushing software radio functions up the mast to the antenna as a viable alternative to the traditional rackmount receiver systems.
The Pentek Model 53641 3U VPX 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D with DDC is also available in the following formats:
The Pentek Model 78690 PCIe L-Band RF Tuner and 2-Channel 200 MHz A/D with Virtex-6 FPGA is also available in the following formats:
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