|Home > Pipeline Vol. 16 No. 2 > Mezzanine Board Strategies for Communication Systems|
Few embedded system applications encompass a more diverse range of frequencies, numbers of channels, data rates, signaling schemes, and signal processing algorithms than communications systems. Apart from this extreme diversity, communication systems must now handle wider signal bandwidths to meet the needs of new complex modulation schemes and higher data rates to support large numbers of channels.
System integrators faced with the task of delivering custom communication systems using COTS board-level products have traditionally relied on mezzanine boards, also known as daughter cards, for modular and flexible interfaces. However, new technologies and mezzanine standards have cast mezzanines for communication systems into complex and critical roles previously handled by other full-size boards in the system. By cutting costs and boosting performance, choosing the right mezzanine boards now becomes a much more significant part of a successful system design.
As shown in Figure 1, the receive section of a modern communication system typically starts with an analog RF stage that amplifies and downconverts the antenna signal to an IF frequency. This IF signal can then be digitized by a wide range of monolithic A/D converters capable of 14- or 16-bit accuracy and sampling frequencies of 100 MHz and higher. The IF signal bandwidth usually covers the entire span of the particular communication band and may contain many different carriers, each at its own frequency.
In order to extract multiple signal channels from this digitized IF band, a digital downconverter (DDC) is required. This process, in turn, starts with a digital local oscillator that produces samples of a sine wave set to the carrier frequency. The samples from the A/D are then mixed with the oscillator samples using a digital multiplier. This translates the carrier signal down to baseband and produces a complex (I+Q) digital signal with upper and lower sidebands centered at 0 Hz. A digital low pass filter, set for the signal bandwidth, removes adjacent channel signals leaving only the channel of interest. Because the bandwidth of the filtered output has been reduced, an output decimator drops the sampling rate commensurate with that bandwidth.
Finally, depending on the type of transmission employed, additional processing steps for demodulating, decoding and decrypting are needed to recover the receive channel data. All of the digital signal processing steps shown in the top half of Figure 1 to the right of the A/D must be repeated for each channel.
On the transmit side, the signal processing steps are exactly reversed, as shown in the lower half of Figure 1. Transmit channel data must first be processed with the appropriate modulation, encoding and encryption to make it compatible with the transmission channel protocols. The digital upconverter (DUC) stage then follows. Here, the digital sample stream signal enters an interpolation filter that preserves the frequency characteristics of the signal, but boosts the sampling rate to match that of the digital mixer and local oscillator. These stages upconvert the baseband transmit signal to the IF frequency. A D/A converter produces an analog IF signal, which is fed into the analog RF transmit section to drive the antenna. All the signal processing steps to the left of the D/A must be repeated for each channel.
Because the A/D and D/A converters generate and require sampled data streams at very high sample rates, general-purpose programmable processors cannot reasonably handle these substantial DSP tasks. Instead, designers often choose ASICs targeted for the specific receive and transmit requirements of the signal channel. However, because of the variety of communication signal types and frequency characteristics, the signal processing tasks tend to be quite unique for each system. As a result, there is no single standard ASIC available to handle a wide range of applications.
Successful mezzanine adoption springs directly from standardization of mezzanine architectures. Standards create win-win situations by assuring customers of multiple vendor availability and competitive prices, and assuring vendors of a viable marketplace worthy of investing in product development. Several popular mezzanine standards emerging in the last few years have hit homeruns. Topping the list is the ubiquitous PMC and its unfolding series of performance enhancements.
A new standard that defines gigabit serial links to mezzanine boards for embedded communication systems is defined in the VITA 42 standard, also known as XMC(1). As an extension to PMC, the XMC specification defines two new connectors that join the mezzanine board to the host or carrier board. At serial bit rates of 3.125 GHz, a dual connector XMC interface supports data rates of 5 Gbytes/sec in each direction.
Although not yet fully adopted, various draft sub-specifications for VITA 42 shown in Figure 2, define the implementation of industry standard switched fabrics. Popular serial fabric clock rates, the number of data lines, and the resulting transfer rates in each direction are shown for either one (J15) or two (J15 and J16) XMC connectors.
Among the first products to take advantage of FPGA technology are mezzanine boards. Because of this, as the features and densities of new FPGA families emerged, they significantly impacted the architectures of communication systems in many different ways. Not only can FPGAs be configured to implement numerous electrical interface standards, they can also implement a variety of communication algorithms such as modulation and demodulation, encoding and decoding, encryption and decryption, and protocol handling.
The offloading of these real-time DSP, logic and bit-rate processing tasks from general-purpose DSP or RISC processors, results in fewer processor boards in the system, and produces significant cost savings. Further, these front-end FPGA engines can extract signal information before it leaves the mezzanine module, thereby resulting in less downstream traffic and lower system data rates.
Since FPGAs can be reconfigured to perform new functions without redesigning the mezzanine board, they can accommodate new communications standards and protocols to help safeguard against product obsolescence, both at the board level and at the deployed system level. When upgrading older communication systems, a single FPGA-based product can replace several legacy products, thanks to improved logic density and flexible interfaces.
As if these benefits were not enough, FPGAs are the primary enabling technology for the new XMC gigabit serial extensions to PMC modules. During the last few years, FPGAs emerged from Xilinx featuring gigabit transceivers called RocketIO MGTs (Multi-Gigabit Transceivers), while Altera offers counterparts dubbed Stratix-GX MGTs. Data channel encoders and decoders support these physical interface drivers and include serial/parallel conversion; this way, data and clock are combined in the signaling on each differential pair over the external serial channel. SERDES (SERializer/DESerializer) blocks built right into the FPGA, include circuitry for both the receive and transmit functions.
A protocol engine within the FPGA interfaces with the SERDES to correctly process packets, header information, control functions, error detection and correction, and payload data format. Since each switched serial fabric standard has its own protocols and rules, FPGAs offer unmatched flexibility by allowing users to install the appropriate IP core protocol engine. The strategy makes FPGA-based XMC modules truly "fabric agnostic" and allows one hardware design to be deployed in several different fabric environments.
By taking advantage of FPGA technology to extend the bandwidth range of the ASIC devices, commercial off-the-shelf mezzanine modules for communication systems can become flexible enough to satisfy a wider range of markets and signal types.
Figure 3 shows a typical software radio transceiver PMC/XMC mezzanine module for communication systems. It features two 14-bit 105 MHz A/Ds and two 16-bit 500 MHz D/As connected to a Xilinx XC2VP50 FPGA. Two ASIC devices handle DDC and DUC functions with memory, timing and system interfaces completing the product. Note that the XMC interface uses the built-in RocketIO gigabit serial transceivers of the FPGA.
The DDC ASIC is a Texas Instruments GC4016 four-channel narrowband device with decimation settings ranging from 32 to 16,384. Since channel bandwidth is inversely proportional to the decimation factor, a factor of 32 limits the maximum usable channel bandwidth to 2.5 MHz(2), falling far short of many communication signal types.
To handle wider signals, two wideband DDC IP cores, installed in the FPGA, with decimation settings ranging from 2 to 64, deliver a maximum channel bandwidth of 40 MHz for both A/Ds. Programmable data switches inside the FPGA allow the wideband DDC cores to be driven directly from the A/D converter or in cascade from the outputs of the GC4016 DDC. This extends the maximum decimation of the GC4016 by a factor of 64. By including the new wideband DDC core, the overall decimation range for the mezzanine now becomes 2 to 1,048,576 instead of the previous 32 to 16,384. This extended range translates directly to an enormous range of input signal bandwidths from 76 Hz to 40 MHz.
The DUC ASIC is a Texas Instruments DAC5686 wideband device with interpolation settings of 2 to 16. Like the DDC, the output channel bandwidth is inversely proportional to the interpolation factor, so with a maximum interpolation setting of only 16, narrowband transmit signals are not supported.
To handle narrowband signals, an interpolation filter is installed in the FPGA with programmable interpolation factors from 16 to 1024. Again, a programmable data switch allows the ASIC DUC to be driven directly from the data interface for wideband signals or from the output of the interpolation filter for narrowband signals. With the interpolation core, the overall interpolation range extends from 2 to 16,384 instead of the previous 2 to 16. Output signal bandwidths from 4.8 kHz to 40 MHz can now be accommodated.
Since all of these critical functions fit in the compact PMC form factor shown in Figure 4, it's easy to see why FPGAs have been so widely deployed on mezzanine modules for communication systems. Of course, many other signal processing tasks, such as those shown in the transmit and receive signal processing blocks in Figure 1, can also be handled by the FPGA.
More sophisticated signal processing operations, such as beamforming, can lead to significant improvements in communication systems. Examples abound along the highway where numerous cellphone towers with vertical antenna arrays, usually in groups of four, can be seen. Signals from multiple receive antennas can be phase-shifted by using the mezzanine module memories as digital delay blocks to enhance reception of a signal arriving from a specific direction. Likewise, transmission using multiple antennas with phase-shifted signals can steer the outgoing signal towards a specific target. This not only provides better service to subscribers but also allows frequency reuse within a cell by dividing the cell into beamformed sectors.
Mezzanines will continue to play important roles in communication systems; they offer an excellent solution to local high-performance signal acquisition and preprocessing, saving costly processor resources in the rest of the system. With FPGAs on board, mezzanines can be reconfigured to meet new communications standards extending the life cycle of existing systems. When new critical ASIC devices emerge, the standardization and modularity of mezzanines supports new technology insertion by simple replacement, rather than scrapping a whole system. This modularity also reduces maintenance, troubleshooting and service costs. Finally, the switched fabric interfaces already available in many mezzanine modules ensure plenty of data bandwidth for future wideband signals.
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