Product Focus: Model 7156 New Software Radio PMC/XMC Captures and Processes Wideband Signals
Features
- Two 400 MHz, 14-bit A/Ds
- One digital upconverter
- Two 800 MHz, 16-bit D/As
- Up to 1 GB of DDR2 SDRAM
- Two Xilinx Virtex-5 FPGAs
- Sample clock synchronization to an external system reference
- LVPECL clock/sync bus for multimodule synchronization
- VITA 42.0 XMC compatible with switched fabric interfaces
- 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O on P14
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General Information
Model 7156 is a dual-channel, highspeed data converter suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters, two Virtex-5 FPGAs and two banks of DDR2 SDRAM. The Model 7156 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces.
A/D Converter
The front end accepts two full-scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications.
The digital outputs are delivered to the Virtex-5 FPGA for signal processing, data capture or routing to other module resources.
Digital Upconverter and D/A
A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages.
When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2, 4, and 8.
Virtex-5 FPGAs
The Model 7156 architecture includes two Virtex-5 FPGAs. The processing FPGA serves as a control and status engine with data and programming interfaces to all of the on-board resources.
A second Virtex-5 FPGA provides the board’s PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing.
Option -104 adds the P14 PMC connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
XMC Interface
The Model 7156 complies with the VITA 42.0 XMC specification for carrier boards. This standard provides, among others, for a x4 link with a 3.125 GHz bit clock between the XMC module and the carrier board. With two x4 links, the 7156 achieves 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.
Clocking and Synchronization
Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths.
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A front panel LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules.
For more details on a special “sales bundle”, click here.
For more information and price quotation on the Model 7156, click here.
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