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Home > Pipeline Vol. 15 No. 4 > Model 6821-422 215 MHz A/D and Digital Receiver Installed Core Printer Friendly Version

Winter 2006/2007 Vol. 15 No. 4   


Model 6821-422 215 MHz A/D and Digital Receiver Installed Core

The Pentek Model 6821-422 Digital Receiver board is based on the popular Pentek Model 6821 215 MHz A/D Converter VME board with installed wideband digital downconverter (DDC) IP cores in each of the board's two Xilinx FPGAs.

The result is a complete, preconfigured digital software radio subsystem that accepts a front-panel analog RF input and delivers real or complex digital output samples translated to baseband from any frequency slice of the input signal.

Applications include wideband recording systems, real-time DSP and software radio systems, and data-acquisition applications for wideband communication signals used in telemetry and SATCOM.

IP Core Compared to ASIC

The FPGA IP Core 422 leapfrogs the commonly used TI/Graychip GC1012B ASIC in speed, dynamic range and programmability. The core operates at frequencies up to 296 MHz and uses higher-precision math than ASIC devices to deliver adjacent channel rejection of up to 100 dB and frequency tuning resolution of 32 bits. The 422 core offers four sets of programmable filter coefficients stored in user-accessible RAM. These coefficients are preloaded during powerup, but can be overwritten during runtime with custom filter characteristics.

Inside the 6821-422

An AD9430 A/D converter digitizes the incoming signal at 215 MHz and delivers identical sample streams to two independent 422 DDC cores, one in each of the XC2VP50 FPGAs. Within each core, an input stage allows scaling of the A/D samples by a 16-bit gain term. Even and odd samples are split into two streams that are directed into two DDC engines operating in parallel. A numerically controlled oscillator (NCO) core generates the desired center frequency of the band of interest. It delivers two complex local oscillator signals to two complex digital mixers that perform frequency translation of the input signal to 0 Hz. Dual FIR lowpass filters limit the output bandwidth. A final combining, decimation and formatting stage delivers real or complex output samples as required. The filters can use one of four independent sets of 18-bit coefficients for each of six decimation settings. The cores also offer a bypass mode that routes the digital samples straight to the output with a simple software switch.

The digital output signals are available on two or four front panel data port (FPDP) connectors using several data-packing modes. In addition, the signals can be delivered as low voltage differential signaling (LVDS) through either the VMEbus P2 connector or a second-slot front-panel mezzanine.

Software Support

The Model 6821-422 is supported by Pentek's C-callable ReadyFlow Board Support Package. ReadyFlow provides development tools for quick startup through application completion, allows programming at high, intermediate and low levels to meet various needs, and includes complete source code for all functions.



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